1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices and methods of producing the same, and more particularly to a semiconductor integrated circuit device including a nonvolatile semiconductor storage device and using a plurality of supply voltages, and a method of producing such a semiconductor integrated circuit device.
A flash memory device is a nonvolatile semiconductor storage device that stores information in the form of electric charges in floating gate electrodes. The flash memory device, which has a simple device configuration, is suitable for forming a large-scale integrated circuit device.
In the flash memory device, information is written or erased by injecting hot carriers into and extracting hot carriers by the Fowler-Nordheim-type tunnel effect from the floating gate electrodes through a tunnel insulating film. Since a high voltage is required to generate such hot carriers, the flash memory device has a voltage rise control circuit that raises a supply voltage provided in its peripheral circuits cooperating with memory cells. Therefore, transistors used in such peripheral circuits have to operate at a high voltage.
On the other hand, it has been practiced of late to form such a flash memory device and a high-speed logic circuit on a common semiconductor substrate as a semiconductor integrated circuit device. In such a high-speed logic circuit, a transistor employed therein is required to operate at a low voltage. Therefore, such a semiconductor integrated circuit device is required to use a plurality of supply voltages.
2. Description of the Related Art
FIGS. 1A through 1Q are diagrams showing a production process of the conventional semiconductor integrated circuit device including such a flash memory and using a plurality of supply voltages.
In FIG. 1A, a flash memory cell region A, a low-voltage operation transistor region B, and a high-voltage operation transistor region C are formed in partitions on a silicon (Si) substrate 11 on which a field oxide film or an isolation structure (not shown in the drawing) such as a shallow trench isolation (STI) structure is formed. In the step of FIG. 1A, a tunnel oxide film 12A of a thickness of 8 to 10 nm is formed on the above-described regions A through C by performing thermal oxidation on the surface of the Si substrate 11 at temperatures ranging from 800 to 1100° C. In the step of FIG. 1B, an amorphous silicon film 13 doped with phosphorous (P) and having a thickness of 80 to 120 nm and an insulating film 14 having a so-called oxide-nitride-oxide (ONO) structure are successively deposited on the tunnel oxide film 12A. The ONO insulating film 14 is formed of a silicon dioxide (SiO2) film 14c of a thickness of 5 to 10 nm deposited by chemical vapor deposition (CVD) on the amorphous silicon film 13, a silicon nitride (SiN) film 14b of a thickness of 5 to 10 nm deposited by CVD on the SiO2 film 14c, and a thermal oxide film 14a of a thickness of 3 to 10 nm formed on the surface of the SiN film 14b. The ONO insulating film 14 has a good leakage-current characteristic.
Next, in the step of FIG. 1C, a resist pattern 15A is formed on the flash memory cell region A, and the ONO insulating film 14, the amorphous silicon film 13, and the tunnel oxide film 12A are removed from the low-voltage operation transistor region B and the high-voltage operation transistor region C on the Si substrate 11 by using the resist pattern 15A as a mask so that the surface of the Si substrate 11 is exposed in the regions B and C. In removing the tunnel oxide film 12A, wet etching using hydrofluoric acid (HF) is performed so that the surface of the Si substrate 11 is exposed to the HF in the regions B and C.
In the step of FIG. 1D, the resist pattern 15A is removed, and a thermal oxide film 12C of a thickness of 10 to 50 nm is formed in the regions B and C to cover the Si substrate 11 by performing thermal oxidation at temperatures ranging from 800 to 1100° C. The thermal oxide film 12C may be replaced by a thermal nitride oxide film.
In the step of FIG. 1E, another resist pattern 15B is formed in the flash memory cell region A to cover the ONO insulating film 14 and in the high-voltage operation transistor region C to cover the thermal oxide film 12C, and the thermal oxide film 12C is removed from the low-voltage operation transistor region B by HF processing by using the resist pattern 15B as a mask so that the surface of the Si substrate 11 is exposed in the region B. By the step of FIG. 1E, the surface of the Si substrate 11 is subjected to the second HF processing in the region B.
In the step of FIG. 1F, the resist pattern 15B is removed, and a thermal oxide film 12B of a thickness of 3 to 10 nm is formed on the exposed Si substrate 11 in the region B by performing thermal oxidation at temperatures ranging from 800 to 1100° C. The thermal oxide film 12B may be replaced by a thermal nitride oxide film. Further, in the step of FIG. 1F, as a result of the thermal oxidation for forming the thermal oxide film 12B, the thickness of the thermal oxide film 12C formed in the high-voltage operation transistor region C increases.
Next, in the step of FIG. 1G, an amorphous silicon film 16 doped with P and having a thickness of 100 to 250 nm is deposited on the structure of FIG. 1F by plasma CVD. The amorphous silicon film 16 may be replaced by a polysilicon film. Further, the amorphous silicon film 16 may be doped with P in a later step. In the step of FIG. 1H, a resist pattern 17A is formed on the amorphous silicon film 16, and by using the resist pattern 17A as a mask, patterning is performed successively on the amorphous silicon film 16, the ONO insulating film 14, and the amorphous silicon film 13 in the flash memory cell region A so that a multilayer gate electrode structure 16F of the flash memory which structure is formed of an amorphous silicon pattern 13A, an ONO pattern 14A, and an amorphous silicon pattern 16A and includes the amorphous silicon pattern 13A as a floating gate electrode is formed in the region A. In the step of FIG. 1G, it is possible to form a silicide film of, for instance, tungsten silicide (WSi) or cobalt silicide (CoSi) on the amorphous silicon film 16 as required. Further, it is also possible to form a non-doped polysilicon film and then form an n-type gate electrode of P or arsenic (As) or a p-type gate electrode of boron (B) or difluoroboron (BF2) in a later step of ion implantation.
Next, in the step of FIG. 1I, the resist pattern 17A is removed, and a new resist pattern 17B is formed to cover the flash memory cell region A. By using the resist pattern 17B as a mask, patterning is performed on the amorphous silicon film 16 in the low-voltage operation transistor region B and the high-voltage operation transistor region C so that a gate electrode 16B of a low-voltage operation transistor and a gate electrode 16C of a high-voltage operation transistor are formed in the regions B and C, respectively.
Next, in the step of FIG. 1J, the resist pattern 17B is removed, and a protection oxide film (also referred to as a protection insulating film or a thermal oxide film) 18 is formed, by performing thermal oxidation at temperatures ranging from 800 to 900° C., to cover each of the multilayer gate electrode structure 16F in the flash memory cell region A, the gate electrode 16B in the low-voltage operation transistor region B, and the gate electrode 16C in the high-voltage operation transistor region C.
Next, in the step of FIG. 1K, a resist pattern 19A is formed on the structure of FIG. 1J so as to cover the low-voltage operation transistor region B, the high-voltage operation transistor region C, and a part of the flash memory cell region A. By using the resist pattern 19A and the multilayer gate electrode structure 16F as masks, ion implantation of P+ is performed typically with a dose of 1×1014 to 3×1014 cm−2 at accelerating voltages ranging from 30 to 80 keV so that an n-type diffusion region 11a is formed next to the multilayer gate electrode structure 16F in the Si substrate 11. P+ may be replaced by As+.
In the step of FIG. 1K, by using the resist pattern 19A as a mask, ion implantation of As+ is performed typically with a dose of 1×1015 to 6×1015 cm−2 at accelerating voltages ranging from 30 to 50 keV so that another n-type diffusion region 11b is formed inside the n-type diffusion region 11a. In the step of FIG. 1K, no ion implantation is performed in the low-voltage operation transistor region B and the high-voltage operation transistor region C since the regions B and C are covered with the resist pattern 19A.
Next, in the step of FIG. 1L, the resist pattern 19A is removed, and a new resist pattern 19B is formed to cover the regions B and C and leave the region A exposed. Further, in the step of FIG. 1L, by using the resist pattern 19B as a mask, ion implantation of As+ is performed with a dose of 5×1014 to 5×1015 cm−2 at accelerating voltages ranging from 30 to 50 keV. As+ may be replaced by P+. As a result, an impurity concentration is increased in the n-type diffusion region 11b and at the same time, a yet another n-type diffusion region 11c is formed in the flash memory cell region A by using the multilayer gate electrode structure 16F as a self-alignment mask. At this point, the step of FIG. 1K may be deleted.
Next, in the step of FIG. 1M, the resist pattern 19B is removed, and a resist pattern 19C is formed on the Si substrate 11 so as to leave only the low-voltage operation transistor region B exposed. Further, in the step of FIG. 1M, ion implantation of a p-type or n-type impurity is performed by using the resist pattern 19C as a mask so that a pair of lightly doped drain (LDD) diffusion regions 11d are formed on both sides of the gate electrode 16B in the Si substrate 11 in the region B with the gate electrode 16B serving as a self-alignment mask.
Next, in the step of FIG. 1N, the resist pattern 19C is removed, and a resist pattern 19D is formed on the Si substrate 11 so as to leave only the high-voltage operation transistor region C exposed. Further, in the step of FIG. 1N, ion implantation of a p-type or n-type impurity element is performed by using the resist pattern 19D as a mask so that a pair of LDD diffusion regions 11e are formed on both sides of the gate electrode 16C in the Si substrate 11 in the region C. The diffusion regions 11d and 11e may be formed in the same step.
Further, in the step of FIG. 10, sidewall insulating films 16s are formed on both sides of each of the multilayer gate electrode structure 16F, the gate electrode 16B, and the gate electrode 16C by depositing and performing etchback on a CVD oxide film. In the step of FIG. 1P, a resist pattern 19E is formed to cover the flash memory cell region A and leave the low-voltage operation transistor region B and the high-voltage operation transistor region C exposed. Further, by performing ion implantation of a p-type or n-type impurity element with the resist pattern 19E and the gate electrodes B and C serving as a mask, p-type or n-type diffusion regions 11f are formed on both sides of the gate electrode 16B in the Si substrate 11 in the region B, and similarly, p-type or n-type diffusion regions 11g are formed on both sides of the gate electrode 16C in the Si substrate 11 in the region C. A low-resistance silicide film of, for instance, WSi or CoSi may be formed as required on the surface of each of the diffusion regions 11f and 11g by silicide processing.
In the step of FIG. 1Q, an interlayer insulating film 20 is formed on the Si substrate 11 so as to continuously cover the regions A through C. Further, in the region A, contact holes are formed in the interlayer insulating film 20 so that the diffusion regions 11b and 11c are exposed, and W plugs 20A are formed in the contact holes. Likewise, in the region B, contact holes are formed in the interlayer insulating film 20 so that the diffusion regions 11f are exposed, and W plugs 20B are formed in the contact holes. In the region C, contact holes are formed in the interlayer insulating film 20 so that the diffusion regions 11g are exposed, and W plugs 20C are formed in the contact holes.
In the production process of the semiconductor integrated circuit device including the flash memory device having the multilayer gate electrode structure 16F, in the step of FIG. 1J, the protection oxide film 18 of a thickness of 5 to 10 nm is formed on the sidewall faces of the multilayer gate electrode structure 16F by thermal oxidation performed at temperatures ranging from 800 to 900° C. As a result of the thermal oxidation, the protection oxide film 18 is formed not only on the multilayer gate electrode structure 16F but also on the sidewall faces of each of the gate electrode 16B formed in the low-voltage operation transistor region B and the gate electrode 16C formed in the high-voltage operation transistor region C as shown in FIGS. 2A and 2B.
At this point, the protection oxide film 18 forms bird's beaks that penetrate under the gate electrode 16B in the region B as shown circled by broken lines in FIG. 2B. Therefore, especially in a low-voltage operation transistor whose gate length is short, that is, whose gate oxide film 12B is thin, a substantial change in the thickness of the gate oxide film 12B is effected right under the gate electrode 16B, thus causing a problem that a threshold characteristic shifts from a desired value.
Indeed, such a problem is prevented from occurring if the protection oxide film 18 is not formed. However, without formation of the protection oxide film 18, electrons retained in the amorphous silicon pattern 13A (hereinafter, also referred to as a floating gate electrode pattern 13A) are dissipated to the sidewall insulating films 16s formed by CVD and etchback in the step of FIG. 10 as shown in FIG. 3B so that information stored in the flash memory device is lost in a short period of time. On the other hand, with the protection oxide film 18 that is a high-quality thermal oxide film hardly allowing a leakage current being formed on the sidewalls of the floating gate electrode pattern 13A, the electrons injected into the floating gate electrode pattern 13A are stably retained therein as shown in FIG. 3A.
Therefore, it is essential to form the protection oxide film 18 in the semiconductor integrated circuit device including the flash memory device. However, formation of such a protection oxide film inevitably causes the problem of a change in the threshold characteristic of a MOS transistor forming a peripheral or logic circuit. Such a problem of a change in the threshold characteristic of the MOS transistor is noticeable when the MOS transistor is a high-speed transistor having a short gate length.
FIG. 4 is a plan view of a configuration of a flash memory cell (flash memory device) having a single-layer gate electrode structure by related art. In FIG. 4, the same element as those of the previous drawings are referred to by the same numerals, and a description thereof will be omitted.
According to FIG. 4, a device region 11A is formed on the Si substrate 11 by a field oxide film 11F. One end of the above-described floating gate electrode pattern 13A is formed on the Si substrate 11 to cross the device region 11A. In the device region 11A, by using the floating gate electrode pattern 13A as a self-alignment mask, the n−-type source region 11a and the n+-type source line region 11b are formed on one side, and the n+-type drain region 11c is formed on the other side.
On the Si substrate 11, another device region 11B is formed next to the device region 11A. An n+-type diffusion region 11C is formed in the device region 11B. The other end of the floating gate electrode pattern 13A is formed as a coupling part 13Ac covering the diffusion region 11C.
FIG. 5A is a sectional view of the flash memory cell of FIG. 4 taken along the line X-X′.
According to FIG. 5A, the tunnel oxide film 12A is formed between the source line region 11b and the drain region 11c on the Si substrate 11, and the floating gate electrode pattern 13A is formed on the tunnel oxide film 12A. Further, the n−-type source region 11a is formed outside the n+-type source line region 11b in the Si substrate 11. The sidewall insulating films 16s are formed on the sidewalls of the floating gate electrode pattern 13A.
FIG. 5B is a sectional view of the flash memory cell of FIG. 4 taken along the line Y-Y′.
According to FIG. 5B, the floating gate electrode pattern 13A continuously extends from the device region 11A to the adjacent device region 11B on the field oxide film 11F formed on the Si substrate 11. The coupling part 13Ac of the floating gate electrode pattern 13A is capacitive-coupled via an oxide film 12Ac to the high-density diffusion region 11C.
At the time of a write (program) operation, by providing the source line region 11b, applying a drain voltage of +5 V to the drain region 11c, and applying a write voltage of +10 V to the high-density diffusion region 11C as shown in FIGS. 6A and 6B, the potential of the floating gate electrode pattern 13A rises so that hot electrons are injected into the floating gate electrode pattern 13A via the tunnel oxide film 12A in the device region 11A.
On the other hand, at the time of an erase operation, an erase voltage of +15 V is applied to the source line region 11b with the drain region 11c and the high-density diffusion region 11C being grounded as shown in FIGS. 6C and 6D. As a result, the electrons in the floating gate electrode pattern 13A tunnel through the tunnel oxide film 12A to the source region 11a to be absorbed into a source power supply through the source line region 11b. 
Thus, in the flash memory cell of FIG. 4, the high-density diffusion region 11C serves as a control gate electrode, and unlike the conventional flash memory cell of a multilayer gate structure, it is unnecessary to form the above-described ONO insulating film 14 between the polysilicon floating gate electrode and the polysilicon control gate electrode. In the flash memory cell of FIGS. 5A and 5B, the oxide film 12Ac serves as the ONO insulating film 14. Since the oxide film 12Ac is formed on the Si substrate 11 by thermal oxidation, the oxide film 12Ac has high quality.
FIGS. 7A through 7M are diagrams showing a production process of a semiconductor integrated circuit device including the flash memory cell of FIG. 4 in addition to the low-voltage operation transistor B and the high-voltage operation transistor C. In the drawings, the same elements as those previously described are referred to by the same numerals, and a description thereof will be omitted.
According to FIG. 7A, the thermal oxide film 12C of a thickness of 5 to 50 nm is formed on the Si substrate 11 by performing thermal oxidation at temperatures ranging from 800 to 1100° C. in each of the flash memory cell region A, the low-voltage operation transistor region B, and the high-voltage operation transistor region C. In the step of FIG. 15B, the thermal oxide film 12C is removed from the flash memory cell region A by a patterning process using a resist pattern 151.
Next, in the step of FIG. 7C, the resist pattern 151 is removed, and the tunnel oxide film 12A of a thickness of 5 to 15 nm is formed on the surface of the Si substrate 11 in the region A by performing thermal oxidation at temperatures ranging from 800 to 1100° C. In the step of FIG. 7C, as a result of the thermal oxidation for forming the tunnel oxide film 12A, the thermal oxide film 12C is developed in each of the regions B and C.
Next, in the step of FIG. 7D, the thermal oxide film 12C is removed from the low-voltage operation transistor region B by a patterning process using a resist pattern 152. Then, in the step of FIG. 7E, after the resist pattern 152 is removed, the thermal oxide film 12B of a thickness of 3 to 10 nm is formed on the exposed Si substrate 11 in the region B by performing thermal oxidation at temperatures ranging from 800 to 1100° C. In the step of FIG. 7E, as a result of the thermal oxidation for forming the thermal oxide film 12B, the tunnel oxide film 12A is developed in the region A and the thermal oxide film 12C is developed in the region C.
Next, in the step of FIG. 7F, the amorphous silicon film 13 uniformly doped with P and having a thickness of 150 to 200 nm is formed on the Si substrate 11. In the step of FIG. 7G, patterning is performed on the amorphous silicon film 13 with a resist pattern 171 serving as a mask, so that the floating gate electrode pattern 13A is formed in the flash memory cell region A, a gate electrode pattern 13B is formed in the low-voltage operation transistor region B, and a gate electrode pattern 13C is formed in the high-voltage operation transistor region C.
Next, in the step of FIG. 7H, the surfaces of the floating gate electrode pattern 13A and the gate electrode patterns 13B and 13C are covered with the protection oxide film 18 of a thickness of 5 to 10 nm by thermal oxidation at temperatures ranging from 800 to 900° C. Then, in the step of FIG. 7I, with a resist pattern 172 serving as a mask, the source region 11a is formed by performing ion implantation of P+ or As+ with a dose of 1×1014 to 5×1014 cm−2 at accelerating voltages ranging from 30 to 80 keV.
Further, in the step of FIG. 7J, with the regions B and C being covered with a resist pattern 173, ion implantation of As+ is performed with a dose of 5×1014 to 3×1015 cm−2 at accelerating voltages ranging from 30 to 50 keV in the region A by using the floating gate electrode pattern 13A as a self-alignment mask. Thereby, the n+-type source line region 11b is formed inside the source region 11a and the n+-type drain region 11c is formed on the opposite side of a channel region from the source region 11a. 
Next, in the step of FIG. 7K, a resist pattern 173 covering the flash memory cell region A is formed, and the LDD regions 11d and 11e are formed in the regions B and C, respectively, by ion implantation of a p-type or n-type impurity element.
Further, in the step of FIG. 7L, the sidewall oxide films 16s are formed on both sidewalls of each of the floating gate electrode pattern 13A and the gate electrode patterns 13B and 13C. In the step of FIG. 7M, with the flash memory region A being covered with a resist pattern 174, the diffusion regions 11f and 11g are formed in the regions B and C, respectively, by ion implantation of a p-type or n-type impurity element.
Also in the production of the semiconductor integrated circuit device including the flash memory device of such a single-layer gate structure, when the thermal oxide film 18 is formed as a protection insulating film to cover the single-layer gate electrode structure (the floating gate electrode pattern) 13A in the flash memory cell region A as shown in detail in FIG. 8A in the step of FIG. 7H, the same thermal oxide film 18 is also formed in the low-voltage transistor region B so as to cover the gate electrode 13B as shown in FIG. 8B. As a result, bird's beaks that penetrate right under the gate electrode 13B are formed as shown circled in FIG. 8B. Therefore, the low-voltage operation transistor formed in the region B is prevented from having a desired threshold characteristic.